This invention relates to a tunable resistance device useful for implementing various analog signal processing functions and, more particularly, to a drain-biassed transresistance device in an active continuous time filter which provides the filter with a tunable frequency response.
In the field of analog signal processing it is important to be able to monolithically generate RC time constants that are accurate, stable and controllable despite variations in process conditions and variations in temperature. The RC time constants determine crucial values such as timing delays and filter frequencies. Accurate RC time constants have been implemented monolithically in VLSI compatible switching technologies such as charge-coupled devices (CCD) and switched-capacitor filters by means of the controlled sampling and transfer of charge packages at a precise clock frequency (f.sub.ck). In the switched-capacitor technique the resistance (R) is generated by data sampling and RC can be made to track a fixed clock frequency (1/f.sub.ck). The switch-capacitor technique has become popular in the MOS analog signal processing field, especially in the development of monolithic filters. One reason for this is that the RC time constants of the basic filter building blocks, such as integrators, can be accurately controlled over varying process and temperature ranges.
Unfortunately, in the switched-capacitor technique accuracy deteriorates rapidly as the signal frequency increases and approaches the clock frequency thereby limiting its utility in high frequency applications. The switched-capacitor technique suffers from a number of drawbacks including, for example, noise folding back into the baseband, the need for antialiasing and smoothing filters, charge injection by the switches, and the presence of switching noise. These drawbacks become more significant as the signal frequency is increased.
In the case of monolithic high frequency applications, continuous time techniques have been gaining in popularity because of the absence of switching problems. Continuous time techniques allow charges to flow continuously in a controlled manner onto a capacitor. The time it takes to charge up this capacitor is used to determine the time constant of the circuit. Two problems to be overcome in such techniques however, are the accurate reproducibility of the RC time constants, and the attainment of a large enough linear operating range so that the signal-to-noise ratio remains sufficiently large. The first of these problems can be solved by using a voltage-controlled active element to generate the R value. Automatic tuning of the RC value is then obtained by means of a phase-locked-loop where the phase of the signal from one such tunable element is compared with that of an external reference clock signal, generally a quartz crystal oscillator. Any difference in frequencies is smoothed out and used as a feedback signal to control the values of other tunable resistor elements. Time constants equal to multiples of the clock frequency can thus be generated. As for the second problem, attempts have been made to linearize the active element. However, the additional circuitry necessary to achieve reliable linearization generally deteriorates the high frequency performance of the circuit.
One solution to the problem of providing a linear tunable resistor element with good frequency performance is to use a MOS transistor as a voltage controlled resistor. By operating a pair of such transistors (M1 & M2) differentially, the second order nonlinear terms in the integrator function can be cancelled. The gate voltage is used to tune or vary the value of R until the correct RC constant is achieved. Such an approach is described on pages 15-29 of an article in the IEEE Journal of Solid State Circuits, vol. SC-21, No. 1, Feb. 1986 by Y. Tsividis et al entitled, "Continuous-Time MOSFET-C Filters in VLSI".
Although accurate and linear operation can be achieved with this last approach, several inherent limitations still exist. First, because both transistors M1 and M2 must remain in their triode regions at all times, the input signal voltage swing must be maintained at least one threshold voltage below the gate voltage. This severely limits the maximum allowable linear range (typically to about 1/3 of the supply voltage), making it necessary to use special pre-scaler and post-scaler circuits. Second, because the input signal is applied to the source-drain junction of the transistor, the input resistance is undesirably low. In an all MOS environment, it is typically difficult to design op-amps that are suitable for driving low resistive loads. Third, to use a PLL technique for automatic tuning typically requires significant chip area, involving such functional blocks as a tunable RC oscillator, a phase comparator and a large smoothing filter.